1. Field of the Invention
The present invention relates generally to the semiconductor technology. More particularly, the invention relates to an improved bonding pad structure in an integrated circuit chip.
2. Description of the Prior Art
An urgent demand for smaller and cheaper electronic products with increased functionality and performance exists. A major trend of circuit design is to incorporate as many circuit components into integrated circuit as possible, whereby cost per wafer can be reduced.
Integrated circuits are manufactured by forming semiconductor devices in the surface of silicon wafers. A multi-level interconnection is formed over the devices, contacting their active elements, and wiring them together to create the desired circuits. The wiring layers are formed by depositing a dielectric layer over the devices, patterning and etching contact openings into this layer, and then depositing conductive material into the openings. A conductive layer is applied over the dielectric layer and patterned to form wiring interconnection between the device contacts, thereby creating a first level of basic circuitry. The circuits are then further interconnected by utilizing additional wiring levels laid out over additional dielectric layers with conductive via.
Depending upon the complexity of the overall integrated circuit, several levels of wiring interconnections are used. On the uppermost level the wiring is terminated at metal pads to which the chip's external wiring connections are bonded. A top metal layer or an aluminum layer may be used in the integrated circuits, for example, for the fabrication of an RF device such as an integrated inductor, a MOM capacitor, a resistor, or a redistribution layer (RDL).
Bonding pads also exist in the top metal layer. During wire bonding process, undesired, conspicuous deformation of the bonding pad occurs due to the stress exerted thereon. The deformed bonding pad may cause the fracture defects in the passivation layer that covers the periphery of the bonding pad. To cope with this problem, the pad opening and/or the space between two pads are typically enlarged. However, increasing the pad opening and the pad pitch results in larger chip size and higher cost.